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  • 100MSps high speed DAQ card for DVS

100MSps high speed DAQ card for DVS


This is a DAQ card specifically tailored for distributed fiber optic vibration sensing systems,14bits dual-channel simultaneous real-time sampling,100MSps sampling rate,Built-in fiber optic sensing and demodulation algorithm.

Model:YB-DVS-100-DAQ
Tags: DVS DAQ 100MSps DAQ fiber optic sensing and demodulation card DVS
Contact:face Huang Email: Hqy@ybphotonics.com
WhatsApp: +8613427781756 Web | App
Get a Quote Manual: Download>>

Product Info


Introduction

This is a data acquisition card for distributed fiber optic vibration monitoring system (DVS) with built-in TTL pulse signal trigger output function to provide signal to the AOM driver, saving extra signal generator (AWG) and reducing the integration difficulty and complexity of the system.

The acquisition card internally uses FPGA to implement fiber optic sensing and demodulation algorithm functions such as exponential amplification, averaging, filtering and power statistics, which are called through dynamic link library (.dll) interface to effectively improve the system processing speed and data difficulty of application software.

This is a PCIe x8 Lane, dual channel, 14bits respectively rate fiber optic sensing demodulation card with 100MSps sampling rate. on board XC7K160T/325T high performance FPGA chip with rich multiplier and RAM resources. By using high-capacity data cache and high-speed data transmission engine technology, it supports real-time upload of raw data with data transmission rate up to 1.2GB/s. The driver has good compatibility and supports multiple versions of WIN7, WIN8 and WIN10 with 32/64bits.


Features

  • 14bits dual-channel simultaneous real-time sampling
  • 100MSps sampling rate
  • DC coupling, 50Ω input impedance
  • 2Vpp input voltage range, 0-60MHz analog bandwidth
  • Up to 88dBc SFDR
  • Trigger output pulse, 16-channel digital IO
  • PCI Express x8 Lane high-speed transfer interface
  • 2GB DDR3 cache
  • Built-in fiber optic sensing and demodulation algorithm


Specifications


Input Channel

Number of input channels
2
Input Impedance
50±1%
Ω
Input Signal Range
2Vp-p/10dBm

Input coupling method
DC(Customizable AC coupling)

Resolution
14
bits
Bandwidth(-3dB)
0-60
MHz
Spurious-free dynamic range(SFDR)
-1dBFS Input/100MSps

fIN=26MHz
88.5
dBc
fIN=42MHz
88.9
dBc
Signal-to-noise ratio(SNR)
-1dBFS Input/250MSps

fIN=26MHz
70
dBFS
fIN=42MHz
72
dBFS
Average noise density
-140
dBm/Hz


Internal Reference Clock

Frequency
10
MHz
Stability
±0.5(-20-60℃)
ppm

Trigger Output

High level minimum voltage
3.3
V
Pulse width resolution
10ns
Minimum pulse width
10ns

Digital Input/Output
Number of channels
16

Leveling standards
3.3V LVTTL

Output drive capability
8(MAX)
mA
Signal Rate
50(MAX)
Mbps
On-Board Cache
2
GB(DDR3L)

Power supply and consumption
  • Power supply voltage: 12V (gold finger power supply)
  • Power consumption: 18W (Max)

Temperature range

  • Working temperature:-20~60℃
  • Storage temperature:-40~85℃

Mechanical dimensions

  • 181mm(L) x 111mm(W)x20mm(D)


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